1. Field of the Invention
The present invention generally relates to dual clock circuits, and, more particularly, to a glitch-free dual clock flow-thru read implementation for use in synchronous Static Random Access Memory (SRAM) devices.
2. Description of the Related Art
Clocks signals are used for timing and synchronization of the internal operations of a computer system. The frequency of the clock signal generally indicates the processing speed of the computer system; the higher the frequency the faster the execution speed.
Most computer systems provide multiple clock signals with different frequencies or phases and it is often necessary to switch among these different clock signals during execution of a program. A glitch signal will arise if the transition between the clock signals does not occur on a clock edge, whether rising or falling. This glitch signal can cause errors during execution of the program since the system components are often unable to complete their operations within the short pulse width of the glitch signal.
In an effort to ensure glitch-free operations in high performance synchronous SRAMs, some have implemented a data set-up requirement for the array data before an output register clock. In order to accomplish this task, however, Read data from the SRAM array may have to wait at an output register until an internally generated clock signal arrives to clock the Read data out to an off-chip driver (OCD). While this ensures glitch-free operations, this required delay slows down the SRAM's total access time.
In another implementation, "old" array data is allowed to propagate through an output latch temporarily, before "new" array data arrives. As a result, the user may experience output data glitches that cause system noise, false data transitions, or access time push-outs, i.e, extra delays in access time.
In light of the foregoing, there exists a need for ensuring glitch-free operations in high performance circuits using dual clocks without causing delays in the circuit operation.